The escalating demands for high density and performance associated with non-volatile memory devices require small design features, high reliability and increased manufacturing throughput. As such, designers continually search for ways to save space on the semiconductor wafer.
Non-volatile memory devices may include a core memory array area where memory cells are formed and a periphery area where periphery (or select) transistors are formed. The select transistors in the periphery area are not commonly formed at the tight pitch at which the memory cells in the core memory array area are formed. As a result, the select transistors are commonly stacked, which consumes valuable space on the semiconductor wafer. Moreover, a transition interface is needed between the select transistors and the core memory array. The transition interface also consumes value space on the semiconductor wafer.